The performance of radio frequency (RF) power devices and integrated circuits (ICs) is particularly sensitive to the terminal impedances associated with connections to the devices or ICs. This is particularly true for metal-oxide-semiconductor (MOS) field-effect-transistors (MOSFETs) and laterally-diffused-metal-oxide-semiconductor (LDMOS) field effect transistors (FETs) where low resistivity substrates (e.g., <0.1 Ohm-cm) are often used to enhance the active device performance. Electro-magnetic (E-M) coupling to such low resistivity substrates can make it difficult or impossible to provide the desired impedance matching at the input-output (I/O) terminals of such devices and preserve the desired power output and efficiency. Further, such E-M coupling can give rise to eddy current losses in the substrate that can further degrade device and IC performance. These problems become more severe with high periphery devices and higher frequency (e.g., >˜1 GHz) devices since the intrinsic device impedance drops with increasing periphery and increasing frequency, and E-M losses increase as the size of the terminal connections (e.g., the bonding pads) increases.
FIG. 1 shows simplified electrical schematic block diagram 10 of field effect transistor (FET) 24 (e.g., a MOSFET) whose gate 14 is coupled to an input bonding pad (IP-BP) 12 by input interconnection 13 and whose drain 16 is coupled to an output bonding pad (OP-BP) 35 by output interconnection 41. At RF frequencies, interconnections 13 and 41 can behave as transmission lines and are accordingly also referred to as input transmission line (IP-TL) 13 and output transmission line (OP-TL) 41. External connection 11 (e.g., a wire bond or other interconnection) sees input impedance Z′in at input bonding pad (IP-BP) 12 and external connection 19 (e.g., a wire bond or other interconnection) sees output impedance Z′out at output bonding pad (OP-BP) 35. Input interconnection (e.g., transmission line (IP-TL)) 13 couples input bonding pad (IN-BP) 12 to MOSFET 24 that has intrinsic input impedance Zin at gate 14, and output interconnection (e.g., transmission line (OP-TL)) 41 couples drain output 16 of FET 24 that has intrinsic output impedance Zout at drain 16 to output bonding pad (OP-BP) 35. FIG. 2 shows simplified equivalent circuit diagram 10′ of block diagram 10 of FIG. 1. Conductances G1, G2, capacitances C1, C2, inductance L1 and resistance R1 represent IN-BP 12. Conductances G3, G4, capacitances C3, C4, inductance L2 and resistance R2 represent IN-TL 13. Transistor 24 is represented by intrinsic impedances Zin and Zout and amplifier A. Conductances G5, G6, capacitances C5, C6, inductance L3 and resistance R3 represent OP-TL 41. Conductances G7, G8, capacitances C7, C8, inductance L4 and resistance R4 represent OP-BP 35.
As the frequency of operation and/or the gate periphery of transistor 24 increase, the intrinsic transistor terminal impedances Zin and Zout becomes smaller, since they scale with frequency and gate periphery. The gate periphery is the twice the sum of the gate width plus gate length, neglecting the slight difference that may exist between gate length and channel length. Gate periphery increases with increasing power handling capability because, effectively, more and more FETS are being operated in parallel. This is visible in various FETS by use of multiple “fingers” coupled in parallel, each finger forming an individual FET. Thus, the decrease in intrinsic impedance is a direct consequence of the need for devices operating at higher power and/or higher frequency, especially for operation at or above about 1 GHz. As the intrinsic impedance Zin and Zout becomes smaller, the parasitic impedances of the interconnections (e.g., IP-TL 13, OP-TL 41) and bonding pads (e.g., IP-BP12 and OP-BP 35) as illustrated in FIGS. 1-2, can become dominant, so that it becomes difficult or impossible to efficiently couple energy into and out of device 24. These parasitic impedances can act as signal stealing voltage dividers. For example, referring now to FIG. 2, the fraction of an input signal presented at terminal 11 that appears at gate 14 to drive transistor 24 is given by the ratio of Zin divided by the sum of Zin plus Z(IN-BP)+Z(IP-TL), where Z(IN-BP) is the series impedance presented by input bonding pad (IN-BP) 12 and Z(IP-TL) is the series impedance presented by input transmission line (IN-TL) 13. With electronic elements represented by block diagram 10 and equivalent circuit 10′ intended for operation at higher frequency and/or higher power (thereby having smaller Zin), the terms Z(IN-BP)+Z(IP-TL) begin to dominate and this voltage divider action reduces the amount of drive that reaches transistor 24. An analogous effect occurs at the output between drain 16 of transistor 24 and output terminal 19. Unless steps are taken to scale the bonding pad and transmission line impedances at the same time as the intrinsic input-output device impedances scale with frequency and/or power handling capability, overall higher frequency operation and higher power handling capability cannot be reasonably achieved.
Thus, a need continues to exist for improved device structures and fabrication methods therefore that reduce the parasitic E-M coupling associated with the terminals and coupling elements of such high frequency devices and ICs, typically the bonding pads and/or interconnections used to couple such high frequency devices and/or ICs to such bonding pads and external leads and/or other components.